The present invention relates to the field of providing clock signals for synchronizing operation of elements of a digital system. More particularly, the present invention relates to providing clock signals for synchronizing operation of elements of a digital interface system between an IEEE 1394 serial bus and a personal computer interface (PCI) device.
Digital systems, such as special purpose logic circuits and general purpose programmable computer systems, typically include a number of elements, such as logic and functional blocks, which operate in synchronism to implement functions of the digital system. Many of these synchronous elements within the system are supplied a clock signal from either a clock generated externally to the system or a local clock generated within the system. This clock signal synchronizes the operation of the synchronous elements so as to propagate control signals and data through the system. The clock signal serves as a timing reference to ensure that each synchronous element executes its operations at an appropriate time and in an appropriate sequence.
A difficultly arises in that a finite amount of time is generally required for the clock signal to propagate from its source to each of the various synchronous elements of the system. Differences between propagation times required for the clock signal to reach each synchronous element become increasingly significant as clock frequencies increase. A further difficulty arises when the digital system must interface with the outside world where timing considerations for this interface are not entirely controlled by the digital system.
A standard adopted by the Institute for Electrical and Electronics Engineers (IEEE), xe2x80x9cIEEE 1394-1995 Standard For A High Performance Serial Bus,xe2x80x9d is an international standard for implementing an economical high-speed serial bus architecture. This standard provides a universal input/output connection for interconnecting digital devices including, for example, audio-visual equipment and personal computers.
The IEEE 1394-1995 standard supports both asynchronous and isochronous format data transfers. Asynchronous transfers are data transfer operations which transfer data from a source node to a destination node and take place as soon as permitted after initiation. An example of an application appropriate for asynchronous data transfer is communication of a still image or text document. Control commands can also be sent asynchronously.
Isochronous data transfers are real-time data transfers which take place such that time intervals between significant instances have the same duration at both the transmitting and receiving applications. An example of an application suitable for the transfer of data isochronously is the transfer of audio-visual data (AV data) between devices, such as a video camera and a television set. The video camera records sounds and images (AV data) and stores the data in discrete segments on tape. Each segment represents the image and/or sound recorded over a limited period of time. The video camera then transfers each segment in a packetized manner during an appropriate interval for reproduction by the television set.
The IEEE 1394-1995 standard bus architecture provides multiple channels for isochronous data communication between applications. A six-bit channel number is broadcast with the data to allow reception by the appropriate application. This allows multiple applications to concurrently communicate isochronous data across the bus structure without interfering with each other.
The cable required by the IEEE 1394-1995 standard is relatively thin in size compared to other bulkier cables used to connect such devices. The IEEE 1394-1995 cable environment is a network of nodes connected by point-to-point links, each link including a port for each node""s physical connection and the cable between them. The physical topology for the cable environment of an IEEE 1394-1995 serial bus is a non-cyclic network of multiple ports, with finite branches. A primary restriction on the cable environment is that nodes must be connected together without forming any closed loops.
Devices can be added and removed from an IEEE 1394-1995 bus while the bus is active. If a device is so added or removed, the bus automatically reconfigures itself for transmitting data between the then existing nodes. A node is considered a logical entity with a unique address on the bus structure. Each node provides an identification ROM, a standardized set of control registers and its own address space.
The IEEE 1394-1995 cables connect ports together on different nodes. Each port includes terminators, transceivers and logic. A node can have multiple ports at its physical connection. The cable and ports act as bus repeaters between the nodes to simulate a single logical bus. The cable physical connection at each node includes one or more ports, arbitration logic, a resynchronizer and an encoder. Each of the ports provide the cable media interface into which the cable connector is connected. The arbitration logic provides access to the bus for the node. The resynchronizer takes received data-strobe encoded data bits and generates data bits synchronized to a local clock for use by the applications within the node. The encoder takes either data being transmitted by the node or data received by the resynchronizer, which is addressed to another node, and encodes it in data-strobe format for transmission across the IEEE 1394-1995 serial bus. Using these components, the cable physical connection translates the physical point-to-point topology of the cable environment into a virtual broadcast bus, which is expected by higher layers of the system. This is accomplished by taking all data received on one port of the physical connection, resynchronizing the data to a local clock and repeating the data out of all of the other ports from the physical connection.
A bus standard commonly utilized for personal computers is known as personal computer interface (PCI). Thus, personal computers typically include an internal PCI bus which operates according to this standard. When a personal computer system is transmitting and receiving data over an IEEE 1394-1995 serial bus, the serial bus must be interfaced to the internal PCI bus. Clock signals must also be provided to synchronize operation.
The invention is a method of and apparatus for providing clock signals for synchronizing operation of elements of a digital interface system between an IEEE 1394 serial bus and a personal computer interface (PCI) bus. The digital interface system includes a number of functional elements in addition to a PCI interface element. Each of the functional elements and the PCI interface element receives a system clock signal via a clock tree. The clock tree derives individual clock signals from the system clock and provides these individual clock signals to each of the functional elements. The clock tree is balanced such that each clock transition occurs at each of the functional elements, other than the PCI interface element, at substantially the same time. Clock balancing is achieved through appropriate circuit layout and insertion of delay elements. The clock tree also derives a clock signal for the PCI interface element from the system clock signal. The portion of the clock tree which provides this clock signal to the PCI interface is not balanced with respect to the remainder of the clock tree. Rather, this portion of the clock tree is conditioned to provide a minimum of delay so as to comply with timing requirements for the PCI bus, such as data set-up and hold times associated with transitions in this clock signal. Accordingly, portions of the clock tree are balanced while at least a portion of the clock tree is not balanced.
According to an aspect of the present invention, an apparatus for synchronizing operation of elements of an interface system between a serial bus and a computer system bus includes an oscillator conditioned to generate a clock signal, a first pathway coupled to the oscillator, wherein the first pathway delivers the clock signal to a first functional element and wherein the first pathway is associated with a first delay for delivering the clock signal to the first functional element, and a balanced plurality of additional pathways, each coupled to the oscillator, wherein the balanced plurality of additional pathways deliver the clock signal to each of a plurality of additional functional elements included in the digital interface system and wherein each of the plurality of pathways is associated with a respective delay for delivering the clock signal to a respective one of the plurality of additional functional elements, wherein the balanced plurality of additional pathways are balanced with respect to each other such that their respective delays are substantially equal and such that each respective delay is longer than the first delay. Preferably, the first functional element interfaces to the computer system bus. In addition, the serial bus can communicate isochronous and asynchronous data packets. Preferably, the serial bus is an IEEE 1394-1995 serial bus. The system bus can be a personal computer interface (PCI) bus.
According to another aspect of the present invention, an apparatus for synchronizing operation of elements of an interface system between a serial bus and a computer system bus includes means for generating a clock signal, first means for delivering coupled to the means for generating, for delivering the clock signal to a first functional element and having an associated first delay for delivering the clock signal to the first functional element, and second means for delivering coupled to the means for generating, for delivering the clock signal to a plurality of additional functional elements included in the digital interface system and having a plurality of balanced delays for delivering the clock signal to each respective additional functional element, wherein the plurality of balanced delays are substantially equal and wherein the first means is configured such that the first delay is shorter than a shortest one of the balanced delays. Preferably, the first functional element interfaces to the computer system bus. In addition, the serial bus can communicate isochronous and asynchronous data packets. Preferably, the serial bus is an IEEE 1394-1995 serial bus. The system bus can be a personal computer interface (PCI) bus.
According to another aspect of the present invention, a method of synchronizing operation of elements of an interface system between a serial bus and a computer system bus includes steps of generating a clock signal, minimizing a delay time for delivering the clock signal to a first functional element of the interface system thereby forming a minimized delay time, and balancing additional delay times for delivering the clock signal to a plurality of additional functional elements wherein the minimized delay time is shorter than the balanced delay times. The method can include a step of communicating data between the serial bus and the computer system bus. Further, the method can include a step of communicating an isochronous data packet via the interface system. Still further, the method can include a step of communicating an asynchronous data packet via the interface system.
According to yet another aspect of the present invention, a computer system includes a system bus, and an interface circuit coupled to the system bus and configured for coupling to a serial bus. The interface circuit includes a system bus interface circuit coupled to the system bus, a plurality of functional elements coupled to the system bus interface circuit for communicating data between the serial bus and the system bus interface circuit, and a clock delivery system coupled to the system bus interface circuit for delivering a clock signal to the system bus interface circuit and having a first delay time for delivering the clock signal to the system bus interface circuit and coupled to the plurality of functional elements for delivering the clock signal to each of the plurality of functional elements and having a plurality of substantially balanced delay times for delivering the clock signal to each of the plurality of functional elements, wherein the balanced delay times are each longer than the first delay time. The serial bus can communicate isochronous and asynchronous data packets. Preferably, the serial bus is an IEEE 1394-1995 serial bus. In addition, the system bus can be a personal computer interface (PCI) bus.
According to another aspect of the present invention, an interface system for communicating data between a serial bus and a computer system bus includes a bus interface circuit for providing an interface to the computer system bus, a plurality of direct memory access (DMA) engines coupled to the bus interface circuit, an internal bus coupled to the DMA engines, a plurality of buffers coupled to the internal bus, a interface device coupled to the plurality of buffers wherein the interface device provides an interface to the serial bus, an unbalanced clock tree for providing a clock signal to the bus interface circuit, to the plurality of DMA engines and to the plurality of buffers wherein delay times for providing the clock signal to each of the plurality of DMA engines and buffers are substantially equal and wherein a delay time for providing the clock signal to the bus interface circuit is shorter than any of the delay times for providing the clock signal to each of the plurality of DMA engines and buffers, and an oscillator coupled to the clock tree for generating the clock signal. The serial bus can communicate isochronous and asynchronous data packets. Preferably, the serial bus is an IEEE 1394-1995 serial bus. The system bus can be a personal computer interface (PCI) bus. In addition, the interface system can include a plurality of aligner circuits, one for each buffer, wherein the aligner circuits are coupled between the internal bus and each respective buffer.